The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device employing a direct sensing technique.
A 16 bit I/O dynamic random access memory (DRAM) and a system LSI having a 32 bit I/O DRAM have been developed. In the near future, a 32 bit I/O DRAM and a system LSI having a 64 bit I/O DRAM will most likey be developed.
A DRAM has a plurality of memory cells. Each cell has a transistor and a capacitor and retains data consisting of "1" and "0". A word line connected to the transistor is activated to transfer a slight charge accumulated in the capacitor to a bit line. A sense amplifier differentially amplifies the slight differential potential at the bit line and transfers the amplified differential potential to a data bus line. Data is read from the memory cell in this manner.
A direct sensing technique is employed to transfer the bit line potential to the data bus line. The direct sensing technique is important for preventing abnormalities that may be caused when increasing the speed of the semiconductor memory device.
FIG. 1 is a schematic circuit diagram showing a prior art DRAM 40 employing the direct sensing technique. The DRAM 40 is provided with a memory array including a matrix of memory cells C. Each of the memory cells C has a capacitor and a MOS transistor and is connected to one of the intersections between the word lines WLi-WLn and the bit line pairs (BLZi, BLXi)-(BLZn, BLXn).
Sense amplifiers 41 are respectively connected to each of the bit line pairs (BLZi, BLXi)-(BLZn, BLXn) to amplify the slight differential potential between the associated pair of bit lines. Each sense amplifier 41 has a CMOS inverter connected between a high potential power supply PSG and a low potential power supply NSG.
A write data bus line WDBiz is connected to the bit lines BLZi-BLZn, and a write data bus line WDBix is connected to the bit lines BLXi-BLXn. Write transistors TN20 are respectively connected between the write data bus line WDBiz and each bit line BLZi-BLZn and between the write data bus line WDBix and each bit line BLXi-BLXn. The gate of each transistor TN20 receives an associated column selection signal WYSELi-WYSELn provided by a column decoder (not shown).
Sets of series-connected read transistors TN21, TN22 are connected between a read data bus line RDBiZ and the ground and between a read data bus line RDBiX and the ground. The gates of each transistor TN22 are connected to the associated bit line pairs (BLZi, BLXi)-(BLZn, BLXn). The gate of each transistor TN21 receives an associated column selection signal RYSELi-RYSELn provided by the column decoder.
The operation of the DRAM 40 will now be described with reference to the timing chart of FIG. 2.
In a cell data read mode, when a word line WL is selected by a word decoder group (not shown) in accordance with a row address, the memory cell transistor connected to the word line WL in each of the memory cells C is activated. This transfers a slight charge to the bit line pairs BLZi-BLZn, BLXi-BLXn. In this state, the power supply PSG and the power supply NSG, each precharged to 1/2 of the Vdd level, are shifted to the high potential power supply Vdd level and the low potential power supply Vss level, respectively, to activate the associated sense amplifier 41. This amplifies the slight potential at the bit line pairs (BLZi, BLXi)-(BLZn, BLXn) to the high potential power supply Vdd level and the low potential power supply Vss level.
After the amplified differential potential at the bit line pairs (BLZi, BLXi)-(BLZn, BLXn) reaches a certain a value, one of the column selection signals, for example, RYSELi is selected by a column decoder group (not shown) in accordance with a column address. This activates the associated read transistors TN21 and transfers the amplified differential potential of the bit line pair BLZi, BLXi to the read data bus line pair RDBiZ, RDBiX. The data is then read from an output circuit (not shown).
In a cell data write mode, if one of the column selection signals, for example, WYSELi goes high after a control signal WE goes high, the associated write transistors TN20 are activated. This transfers data from the write data bus line pair WDBiZ, WDBiX to the bit line pair BLZi, BLXi via the write transistors TN20 and writes the data to the associated memory cells C.
In the DRAM 40, which employs the direct sensing technique, the sense amplifiers 41 are spaced from the data bus line pair WDBiZ, WDBiX, which have a large load. Thus, the load on the sense amplifiers is small. This permits high speed operation during the read mode. However, the read data bus line pair RDBiZ, RDBiX and the write data bus line pair WDBiZ, WDBiX are provided separately. Further, the write and read column selection lines are provided separately. This increases the size of the data bus section and, consequently, the chip area.
Enlargement of the DRAM and an increase in the number of I/Os increases the number of I/O-related read data bus line pairs RDBiZ, RDBiX and write data bus line pairs WDBiZ, WDBiX. Therefore, employment of the direct sensing technique results in large increase in the chip area.
FIG. 3 shows a DRAM 50 described in Japanese Unexamined Patent Publication No. 6-302190 that has a decreased area. The DRAM 50 uses a data bus line pair DBiZ, DBiX, which functions as both the write data bus line pair WDBiZ, WDBiX and the read data bus line pair RDBiZ, RDBiX.
However, the DRAM 50 still uses separate lines for the read column selection signals RYSELi-RYSELn and the write column selections signals WYSELi-WYSELn. This hinders further reduction in the data bus area.
As shown in FIGS. 4 and 5, the read column selection signals RYSELi-RYSELn and the column selection signals WYSELi-WYSELn are generated by a column decoder 51 in accordance with a write control signal WE from a write control circuit 52 and address signals Ai-An from an address buffer 53.
The DRAM 50 includes a plurality of memory cell arrays 54 (FIG. 5), each being provided with the column decoder 51. Accordingly, a line for transferring the control signal WE from the write control circuit 52 must be laid out along each column decoder 51. This increases the total line capacitance, which includes the parasitic capacitance Q1 of the lines and the gate capacitance Qg of the logic gates. As a result, power is consumed inefficiently and high speed read and write operations are interfered with.